1. Field of the Invention
The present invention relates to the memory field. More specifically, the present invention relates to the refresh of memory devices.
2. Description of the Related Art
Memory devices are commonly used to store data in a number of applications; particularly, in a non-volatile memory device the data is preserved even when a power supply is off. Typically, the memory device includes a matrix of memory cells (for example, consisting of floating gate MOS transistors). The memory cells are programmed by injecting electrical charge into their floating gates; conversely, the memory cells are erased by discharging the floating gates. The electrical charge in the floating gate of each memory cell defines different levels of its threshold voltage representing corresponding logical values. Particularly, in a multi-level memory device each memory cell can take more than two levels (and then store a plurality of bits).
The logical values stored in memory cells selected by a corresponding address are read by comparing a current flowing through each selected memory cell with the currents provided by reference cells having predefined threshold voltages. As such, a suitable biasing voltage is applied to the selected memory cells and to the reference cells. In a specific reading technique (as described in U.S. Pat. No. 7,054,197, the entire disclosure of which is herein incorporated by reference) the biasing voltage has a ramp-like time pattern. In this case, the selected memory cells and the reference cells turn on at different times (as soon as the biasing ramp reaches their threshold voltages). The temporal order of the turning on of each selected memory cell with respect to the ones of the reference cells uniquely identifies the logical value stored in the selected memory cell. In this way, the precision of the read operation is strongly improved and made independent of most external factors.
A very critical problem of the memory devices known in the art is their data retention. In fact, the memory cells are subjected to different electrical stresses during operation of the memory devices; these stresses may cause a partial loss of the electrical charge stored in their floating gates, with an undesired erasure of the memory cells that may even cause a change of the logical values stored therein. This problem is particular acute in modern memory devices, wherein the memory cells have very thin oxide layers. Moreover, the problem is exacerbated in multilevel memory devices, wherein the gap between adjacent levels of the threshold voltages is strongly reduced (down to 0.3V); in this case, even a small drift of the threshold voltages of the memory cells (for example, of 0.1V) may change their logical values.
The above-mentioned problem may be addressed by the use of Error Correction Code (ECC) techniques. The ECC adds redundant control information to blocks of logical values (for example, consisting of pages formed by 64 bits). This control information is used for detecting and correcting (if possible) errors in the pages. This allows tolerating some drifts of the threshold voltages of the memory cells without impairing operation of the memory device.
Nevertheless, the structures used to implement the ECC involve a considerable waste of space for storing the control information. Furthermore, the operations required to manipulate the control information slow down operation of the memory device. In addition, the data can be written to and read from the memory device at the level of pages only (because of the need to process the corresponding control information).
A different solution for preventing the loss of data stored in the memory cells is of refreshing their content. For example, it is possible to copy a sector of the memory device onto a volatile memory device, erasing the sector, and then restoring the data from the volatile memory device; however, any power supply cut during the refreshing operation would cause the complete loss of the data stored in the volatile memory device, and then the impossibility of restoring it onto the non-volatile memory device.
The refresh operation may also be performed individually for each memory cell (directly on the memory device). The threshold voltage of the memory cell is compared with both read references (discriminating the different logical values that can be stored therein) and corresponding guard references (each one slightly higher than a corresponding read reference). In this way, a warning condition of the memory cell can be detected when its threshold voltage is comprised between any read reference and the corresponding guard reference (meaning that the memory cell has lost electrical charge and then it is dangerously approaching the read reference of its logical value). In this case, a soft-program pulse is applied to the memory cell, so as to inject a small amount of electrical charge into its floating gate (until the correct threshold voltage of the memory cell over the guard reference has been restored).
The refresh operation is typically performed periodically (for example, after a predetermined number of operations executed on the memory device). Alternatively, it has also been proposed to verify the condition of each memory cell whenever it is read; in this case, the memory cell is refreshed immediately after the read operation (when it is necessary). For example, this technique is described in EP-A-1271552.
In any case, the refresh operation takes a relatively long time. Particularly, the choice of performing it periodically requires stopping operation of the memory device for the whole period that is necessary to refresh all the memory cells; therefore, this procedure may be untenable in most practical situations. Conversely, when the memory cells are refreshed after their reading the corresponding access time is significantly increased (since the memory cells are not available until completion of the refresh operation); this has a detrimental impact on the performance of the whole memory device.
All of the above limits the application of the refresh operation; therefore, this may impair the reliability of the memory device.